In 1965, Gordon Moore made a simple observation: every year or two, the number of parts you could put on one chip, at a reasonable price, doubled. Notice what he did not say. He did not say transistors must get smaller. Smaller was just how the industry chose to deliver the doubling — and for sixty years it was the only way anyone knew. That distinction matters now, because the shrinking has gotten very hard, and everyone forgot it was only ever a means to an end.

The road that narrowed

The trouble with shrinking is money before it is physics. A leading-edge 3 nm wafer sells for about $19,500. A mature 28 nm wafer sells for about $3,000. The advanced wafer packs roughly 87× more transistors, so the math still works — if you can get in the door. But the door is the problem. The lithography machines cost hundreds of millions each. A new fab costs over twenty billion. Designing one chip costs hundreds of millions more. And the capacity is booked years ahead by a handful of giants. Transistors still get cheaper at the leading edge; they just don't get cheaper for you. A law of progress that only three companies can use isn't dead — but it isn't a law anymore. It's a subscription.

Memory already found the exit

The way out has been sitting in every SSD for a decade. Flash memory hit its own shrinking wall around 2012: the cells got too small to hold their charge. The industry's answer was not a better shrink. It was a 90-degree turn. 3D flash stacked the memory cells vertically — 24 layers in 2013, more than 300 today. Nobody misses flat flash, because bits kept getting cheaper. Just in a new direction.

Computing chips never made that turn, and the reason is heat. Making a silicon transistor takes temperatures near 1,000 °C. But the copper wiring on a finished chip is ruined above about 450 °C. So you can build one layer of transistors and wire it up — and then you are stuck. Build a second layer on top, and the heat destroys the first. That one number, 450 °C, is why computing stayed flat for the decade memory went vertical. Gluing finished chips on top of each other helps a little. But glued chips talk through solder bumps: big, coarse connections, tens of microns apart. Good enough to pass messages. Nowhere near good enough to put a memory cell directly above the transistor that reads it.

A transistor you can grow at 450 °C

This is the wall that 2D semiconductors break. These are materials — molybdenum disulfide is the workhorse — that form a working transistor in a sheet just three atoms thick. And they can be grown as a film at temperatures the wiring below survives. Our growth machine uses plasma and light, instead of heat, to drive the chemistry. So a new layer of transistors goes down on top of a finished chip like a coating, and the chip underneath never notices. Each layer is a third of a micron thick, connected downward by vertical wires as fine as the circuits themselves: millions of connections per square millimeter, where glued stacks manage thousands.

Sophon, our reference design, stacks 64 of these layers — 32 for computing, 32 for memory — on an ordinary 28 nm silicon base. The whole stack is 22.4 microns tall: less than half the thickness of a single die in an HBM memory stack. Computing can finally do what flash memory did twelve years ago.

The arithmetic of the second axis

The math is short. Shrink a transistor, and density grows with the square of the shrink. Stack layers, and density grows with the layer count — and the physics puts no ceiling on the count. The two combine into one rule: divide the process node by the square root of the layer count, and you get the chip's effective node. Sixty-four layers at 28 nm: 28 ÷ 8 = 3.5. Read that again. A process from 2011, stacked 64 high, has the same effective transistor density as the most advanced chip money can buy. On wafers that cost 6.5× less. From fabs with idle capacity. With no EUV machine anywhere in the building.

The trade works at every node, and the chart below puts both roads on one map. Read the gap between the lines: it is exactly the number of layers heat allows, and it narrows as the node shrinks, because each layer burns more power on a finer process. That gives the ceiling a peak near 5 nm — and gives the second axis its home ground on mature nodes, where the fabs are open. Our roadmap rides far below the ceiling: 64 layers today, never more than 144, and still a 1.2 nm-class effective node on a 7 nm base by 2036.

Logic density versus process node from 55 nm to 1.4 nm Log-log plot from 55 nm to 1.4 nm. A dashed gray planar silicon curve rises from 0.4x at 55 nm to 82x at A14. A dotted blue thermal-limited stacking ceiling equals max layers times the same node’s planar density: 120x at 55 nm where the 300-layer anneal budget caps stacking, 258x at 28 nm, peaking near 1,890x around 5 nm, then declining to 1,148x at 1.4 nm as the layer limit falls to 14. The vertical gap between the lines equals the layer count. Dark markers pin the announced NVIDIA and AMD roadmap onto the planar curve: Rubin 2026 and Rubin Ultra 2027 at 3 nm-class, AMD MI500 2027 at 2 nm-class, and Feynman 2028 at A16. Logic density vs process node: the planar curve, and the ceiling above it 1× 10× 100× 1,000× N7 N3 N2 A14 planar silicon (published density) 300 layers (anneal-capped) 258 221 165 103 72 51 31 21 14 thermal-limited stacking ceiling thermals erode the stacking dividend at the leading edge ×258 layers — the second axis 55 28 16 10 7 5 3 2 1.4 process node F, nm (log · shrinking →) planar: published logic densities relative to 28 nm — the curve flattens as node names outrun geometry ceiling: max stacking before the 65 K junction budget, 400 W/cm² cold plate, and 450 °C anneal budget bind · no EUV anywhere numbers = max layers — exactly the vertical gap between the lines; per-tier power rises as F shrinks, so the roads converge Rubin '26 R. Ultra '27 MI500 '27 Feynman '28 (A16) — the road the NVIDIA / AMD roadmap rides ('26–'28 marked)
One basis for both lines: the ceiling is max layers × the same node's published density, so the vertical gap between the curves is the layer limit itself — 300 at 55 nm (the one point capped by the 450 °C anneal budget rather than heat), 258 at 28 nm, 14 at 1.4 nm. Past the peak near 5 nm, per-layer power rises faster than per-layer density and the ceiling rolls over. Nothing on this chart needs EUV. Dark markers: the announced NVIDIA / AMD roadmap — Rubin '26 and Rubin Ultra '27 (3 nm-class), MI500 '27 (2 nm-class), Feynman '28 (A16) — all of it on the planar curve.

Energy tells the same story. Run at the same low voltage, an older node's arithmetic costs only about twice the energy of the leading edge's. But the layers do something shrinking never did: they put every piece of data a few hundred nanometers above the circuit that uses it. Moving data — not doing math — is what dominates AI power bills, and the vertical road simply deletes the trip. Density is what stacking promises. Proximity is what it quietly delivers.

What the vertical road is paved with

The old road was paved with lithography machines. The new one is paved with growth steps: each layer costs one deposition and one patterning pass at mature-node prices, about $52 per layer per chip. The toll is yield. Every layer you add multiplies the chip's survival odds by 99.7%, and that compounds, so stacks have a sweet spot. Too few layers, and the fixed costs dominate. Too many, and the failures do. Pure cost-per-performance favors about 24 layers; Sophon ships 64, paying an 8% premium to carry 330 GB of model memory on the chip itself. There is no free lunch here — just ordinary process engineering, with knobs and trade-offs. What there isn't is nation-state lithography.

Dollars per thousand tokens per second versus process node at the thermal stacking ceiling Log-log chart of modeled cost per 1,000 tokens per second for Sophon designs built at each node’s thermal-limited layer count, matching the density chart: 4,719 dollars at 55 nm with 300 layers, 1,019 at 28 nm with 258, 279 at 16 nm, 109 at 10 nm, 62 at 7 nm, 50 at 5 nm, 16 at 3 nm, 12 at 2 nm, and 7 dollars at 1.4 nm with 14 layers. A dashed line near 190,000 dollars marks 2026 HBM4 flagship GPUs at market price; an arrow labels the over-four-order gap as architectural. Dark diamonds mark the projected GPU roadmap: Rubin Ultra in 2027 near 220,000 dollars at 3 nm-class and Feynman in 2028 near 230,000 dollars at A16, modeled from analyst package prices, a flat trajectory. Dollars per 1,000 tokens/s vs process node (80B decode, batch 1) $10 $100 $1,000 $10,000 $100,000 2026 HBM4 flagships (Rubin / MI455X · market price ≈$180–200k) $4,719 $1,019 $279 $109 $62 $50 $16 $12 $7 Sophon at the stacking ceiling (modeled BOM) over four orders of magnitude architecture, not node 55 ×300 28 ×258 16 ×165 10 ×103 7 ×72 5 ×51 3 ×31 2 ×21 1.4 ×14 process node, nm (log) · ×N = max layers, same as the density chart Sophon: modeled BOM ÷ batch-1 decode at the thermal-ceiling layer count (≈1.6–3 kW peak per die) · Murphy yield × 0.997ⁿ 2 nm / 1.4 nm wafer prices estimated ($30k / $38k) · HBM line: market price ÷ bandwidth-bound batch-1 decode '27 '28 NVIDIA / AMD roadmap ('26 → '28): flat Rubin $183k → R. Ultra ~$220k → Feynman ~$230k HBM price grows with the bandwidth '27–'28 points: analyst prices ÷ HBM-bound decode (R. Ultra 40 TB/s HBM4e · Feynman ~32 TB/s HBM5) · AMD MI500 '27: specs undisclosed
What the toll adds up to, at the same layer counts as the density chart: modeled BOM per 1,000 tokens/s for a die built to each node's thermal ceiling — $4,719 at 55 nm (300 layers, mostly yield burden) falling to about $7 at 1.4 nm (14 layers). The shipping 64-layer product lands at $579; 2 nm and 1.4 nm use estimated wafer prices. The dashed line is what 2026 HBM4 flagships cost per 1,000 tok/s at market price; the dark diamonds carry that roadmap forward on analyst price estimates — Rubin Ultra ('27) near $220k, Feynman ('28) near $230k — flat, because each HBM generation arrives priced roughly in proportion to its bandwidth. Node choice moves the blue line by ~670×; the jump from the dashed line down to blue is the architecture.

And the vertical road carries something the old one never did. Sixty years of shrinking made computing fast while memory access stayed slow — the memory wall every chip designer fights is the old road's accumulated toll. Stacking builds the memory into the chip itself. Sophon's 32 memory layers hold 330 GB and deliver 2.10 petabytes per second inside the chip: about 100× what the best memory package on the market feeds a GPU. The reason is simple. The memory is not sitting next to the processor; it is sitting 14 microns above it. The old road made transistors cheap and left data movement expensive. The new one makes integration cheap. And integration — not transistor count — was always the thing Moore was measuring.

Sophon's figures are modeled engineering targets from a complete published design, not measurements from shipping silicon; the whitepaper carries every equation and every risk in the open.

Moore's paper never said which direction the components had to multiply in. For sixty years there was only one direction available. Now there are two, and the second one is open to any fab built since 2011.

Frequently asked questions

Is Moore's law dead?
The geometric version — double density by shrinking transistors — is economically exhausted for everyone except the leading-edge few. The economic version — double what you can integrate per dollar — has a second axis: layer count. Stacking transistor layers on mature nodes continues the economic law without EUV.
Why couldn't logic stack vertically before, when 3D NAND has shipped since 2013?
Temperature. Silicon transistors require processing near 1,000 °C, and the copper wiring of any finished layer beneath is destroyed above roughly 450 °C. 3D flash memory sidesteps this with a specialized memory-only process that logic cannot use. 2D semiconductors grown below 450 °C are the first logic-grade transistors that can be built on top of finished, wired circuits.
What limits how many tiers can be stacked?
Three ceilings: yield (each layer multiplies a chip's survival odds by 99.7%, and it compounds), the total heat the bottom layer's wiring can absorb across hundreds of growth steps (roughly 300 layers), and getting the heat out of the stack. Economics bind first: the cost sweet spot at 28 nm sits near 24 layers, and the roadmap keeps stacks between 36 and 144 layers while the node shrinks underneath.